Senior Logic Verification Engineer

Design Engineering (ASIC, IP) Da Nang, Vietnam

Summary
• eSilicon has revolutionized the chip business by partnering with tier-one suppliers to streamline the IC design and manufacturing processes, bringing our customers' chips to market faster. eSilicon has a world-class custom IP team with a successful track record of first-time silicon success and demonstrated ability to provide niche IP and design services at leading-edge process nodes.
• Our Analog Mixed Signal IP Team is seeking for Senior FrontEnd Design/Verification to join our talented team.
• We are working on most advanced product on the market. Join us and make a difference.
Opportunities
• Work with highly experienced global team and talented highly motivated Viet Nam engineering team
• Work in a professional, innovative and fun environment.
• Working on most competitive designs such as: High Band Width Memory (HBM) PHY, High Speed PAM4 56G/128G Serdes, High Band Width Die to Die PHY..
• Opportunity to get in touch with the complete flow of a real complicated Analog Mixed Signal Design: From Specification - RTL/Synthesis - Analog Circuit/Layout – Place & Route – Timing & Physical Sign Off - Packaging – Signal/Power Integrity – Silicon Bring Up.
• Chance to work with the latest possible technology nodes (16nm/14nm/10nm/7nm/5nm) from all foundries.
• Clear career path of self-development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe and Asia for demo shows, customer engagement, training and on site support.

Benefits
• Competitive salary
• Very good insurance program for engineer and family members
• Strong internal training programs of softskills
• Participate in valuable conferences to learn and share knowledge with IC design community

Responsibilities
• Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architect
• Create and enhance constrained-random verification environments using SystemVerilog and UVM/VMM
• Debug tests with design engineers to deliver functionally correct design blocks.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Participate in building and enhancing flow for faster, higher quality design process.
• Work closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows
• May lead a front-end team to complete a full project
• May mentor junior engineers or interns.

• BS in Electronics Engineering, Electromechanics, Telecommunications.
• 4+ years of experience in front-end jobs.
• Experience with writing and execution of detailed verification test plan.
• Verification experience in any of the protocols like USB/PCIe/DDR or other complex protocols is highly desirable.
• Experience developing directed test & random test environment using System-Verilog/UVM/VMM
• Experience with System Verilog Assertion (SVA).
• Experience with Gate Level simulation & timing back-annotation simulation.
• Experience with analysis/closure of code and functional coverage.
• Experience with scripting language such as Python or Perl and EDA Verification tools, as well as bug tracking and regression mechanisms.
• Familiarity with Post-Silicon validation and debug.
• Have basic knowledge about Synthesis, STA, Formality is an plus.
• Locate in Danang city
• Good English communication

- Training with Trainers from U.S

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