Senior / Junior Physical Design (PD) Engineer

• Following standard practices, implement and verify deep sub-micron multi-million gate SoC (System on Chip) ASIC Designs;
• Working as part of a team and under closer supervision, tasks include but are not limited to synthesis of RTL netlist, development, design and implementation of top/block level floor-plans;
• Performance of clock-tree synthesis and high fan-out net synthesis;
• Plan place and route architecture; conduct static timing analysis. Implement DRC, LVS and Antenna;
• Determine the cause of any potential cause for gate array failure, ensuring parasitic extraction; and, perform design validation and provide formal verification.

1. Senior PD Engineer
• Bachelors or Master’s degree in Engineering with 3+ years of ASIC physical design ( place and route ) experience;
• Proven APR hands-on tapeout ASIC experiences in 45nm and/or below technologies, fluent with Netlist-to-GDS flow using Sysopsys/Cadence tools;
• Experienced to be an APR block owner or top-level integration/floorplanning/ APR engineer;
• Must be able to work independently, to collaborate with different teams, and to be flexible to take dynamic and challenging assignments. Must have good communication skills, and can take tapeout pressure;
• Experienced in Tcl/Perl scripting to innovate APR methodology;
• Low power implementation;
• Familiar with synthesis (RTL to Netlist);
• Experience in digital design flows including RTL synthesis, STA, PNR and Physical Verification. Experience with Cadence, Synopsys tools a plus;
• Preferred if you have managed a team of Physical Design Engineers;
• Strong understanding of LINUX & windows operating systems;
• Programming experience with Tcl, Perl, and Shell;
• Strong written and verbal communication skills.

2. Junior PD Engineer
• In the last year of undergraduate program in Electronics Engineering or Physics Engineering or with working experience of 1-2 years.
• Strong analytical, logical thinking, debugging skills.
• Good understanding of Fundamentals of Synchronous logic design.
• Good communication skills, positive attitude, and ability to work in a team environment.
• High GPA score (7.0 and above)
• A good command of English.
• Exposure to a scripting languages such as TCL, Perl, and/or C-shell is a plus.
• Prefer to working in Linux environment.
• Coursework in digital IC design is a plus.
• Prefer to experiencing with Verilog coding and verification.
• Project or industry experience in ASIC (Backend design: DFT, Layout, STA) is a plus.
• Prefer to understand process window & variation in semiconductor design

- 13th month salary
- Healthcare
- Performance bonus

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