Implementation (Synthesis, Timing) Design Engineer (Competitive Salary and Benefit)
Mức lương: Thỏa thuận
Đã hết hạn nộp hồ sơ - 196 lượt xem
Ngày cập nhật: 12/09/2019
Thông Tin Tuyển Dụng
Mô tả công việc
In this role, you will be responsible for ASIC implementation, including synthesis, floorplanning, timing closure, on our cutting edge ARMv8 based server on chip solutions (X-Gene) that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology (16nm and 7nm) nodes available in the industry.
Responsibilities:
• Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, and other frontend sign-off.
• Run netlist and physical synthesis on large and medium size blocks.
• Implement and verify other aspects netlist generation like scan-insertion, clock-gating checks, power-domain checks, etc.
• As part of the team, develop front-end implementation flows on synthesis, verification, timing analysis, eco-generation, etc.
• Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners.
• Perform timing closure across all corners to ensure successful tapeout following our aggressive deadlines.
• Generate and implement functional ECO.
• Run Logic Equivalent Check (LEC) from RTL to prelayout/postlayout netlist.
Responsibilities:
• Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, and other frontend sign-off.
• Run netlist and physical synthesis on large and medium size blocks.
• Implement and verify other aspects netlist generation like scan-insertion, clock-gating checks, power-domain checks, etc.
• As part of the team, develop front-end implementation flows on synthesis, verification, timing analysis, eco-generation, etc.
• Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners.
• Perform timing closure across all corners to ensure successful tapeout following our aggressive deadlines.
• Generate and implement functional ECO.
• Run Logic Equivalent Check (LEC) from RTL to prelayout/postlayout netlist.
Yêu cầu ứng viên
Qualifications:
• 2-7 years of digital ASIC design/verification experience.
• Experience with Verilog or HDL languages and tools.
• Experience in scripting languages (PERL, TCL, shell, etc.)
• Experience in ASIC methodologies and tools like RTL Compiler, Synopsys Primetime, Cadence Tempus, LEC, CDC, etc.
• Physical design experience a plus.
• Timing analysis and synthesis experience a plus.
• Good communication and teamwork skills.
• Good English and Vietnamese communications skills, both speaking and writing.
Education:
• BS/MS/Ph.D. in Electrical Engineering/Computer Engineering or equivalent.
• 2-7 years of digital ASIC design/verification experience.
• Experience with Verilog or HDL languages and tools.
• Experience in scripting languages (PERL, TCL, shell, etc.)
• Experience in ASIC methodologies and tools like RTL Compiler, Synopsys Primetime, Cadence Tempus, LEC, CDC, etc.
• Physical design experience a plus.
• Timing analysis and synthesis experience a plus.
• Good communication and teamwork skills.
• Good English and Vietnamese communications skills, both speaking and writing.
Education:
• BS/MS/Ph.D. in Electrical Engineering/Computer Engineering or equivalent.
Quyền lợi được hưởng
- Competitive Salary and Benefits
- PVI insurance for employee and family
- Business travel opportunity to abroad
- PVI insurance for employee and family
- Business travel opportunity to abroad
Cách thức ứng tuyển
Hồ sơ theo yêu cầu của nhà tuyển dụng khi liên hệ trực tiếp
Giới thiệu về công ty
AMPERE COMPUTING VIETNAM
Incubation Building, Lot D.01, Tan Thuan Street, Tan Thuan Export Processing Zone, Tan Thuan Dong Ward, Dist 7, HCMC
Incubation Building, Lot D.01, Tan Thuan Street, Tan Thuan Export Processing Zone, Tan Thuan Dong Ward, Dist 7, HCMC
Ampere is leveraging the depth and expertise within the cloud and semiconductor industries to push the boundaries of emerging cloud applications. Our world class team of scientists are focused on the development of new semiconductor designs and building out the first software ecosystem for Arm®-based server processors. We give our ...Chi tiết
Ampere is leveraging the depth and expertise within the cloud and semiconductor industries to push the boundaries of emerging cloud applications. Our world class team of scientists are focused on the development of new semiconductor designs and building out the first software ecosystem for Arm®-based server processors. We give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications. Ampere Computing’s Headquarters are located in Santa Clara, California, USA. Sales and Engineering offices are located throughout the world. Vietnam Design Center provides good compensation and benefit programs and working conditions. Company website: http://www.amperecomputing.com Ẩn chi tiết
Bạn đang xem tin việc làm Implementation (Synthesis, Timing) Design Engineer (Competitive Salary and Benefit) trong ngành được tuyển dụng tại bởi AMPERE COMPUTING VIETNAM. AMPERE COMPUTING VIETNAM đang cần tuyển 0 người nhân sự với hình thức làm việc: Toàn thời gian cố định. Yêu cầu kinh nghiệm Không yêu cầu. Website tìm việc làm timviec24h.vn cập nhật tin Implementation (Synthesis, Timing) Design Engineer (Competitive Salary and Benefit) cách đây lúc 07/11/2019 00:00:00. Người tìm việc lưu ý không nên đặt tiền cọc khi xin việc . Chúng tôi luôn cố gắng đưa tin tức tuyển dụng nhanh và chính xác nhất cho bạn.
AMPERE COMPUTING VIETNAM
Địa chỉ: Incubation Building, Lot D.01, Tan Thuan Street, Tan Thuan Export Processing Zone, Tan Thuan Dong Ward, Dist 7, HCMC
Quy mô: 100-499 nhân viên
Việc làm tương tự
Implementation (Synthesis, Timing) Design Engineer (Competitive Salary and Benefit)
Mức lương: Thỏa thuận | Hạn nộp hồ sơ: Đã hết hạn nộp hồ sơ