DFT Engineer (At All Levels)

• Following standard practices, implement and verify deep sub-micron multi-million gate SoC (System on Chip) ASIC Designs;
• Working as part of a team and under closer supervision, tasks include but are not limited to synthesis of RTL netlist, development, design and implementation of top/block level floor-plans;
• Performance of clock-tree synthesis and high fan-out net synthesis;
• Plan place and route architecture; conduct static timing analysis. Implement DRC, LVS and Antenna;
• Determine the cause of any potential cause for gate array failure, ensuring parasitic extraction; and, perform design validation and provide formal verification.

1. Experienced DFT Engineer
• 3+ years of DFT experience, leading DFT efforts for SOC designs;
• Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time;
• Experience developing DFT specifications and driving DFT architecture and methods for designs a plus;
• Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools;
• Knowledge of industry standards DFT and design tools;
• Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues a plus;
• Experience with STA constraints development and analysis for DFT modes and SDF simulations a plus.

2. Junior DFT Engineer
• In the last year of undergraduate program in Electronics Engineering or Physics Engineering or with working experience of 1-2 years.
• Strong analytical, logical thinking, debugging skills.
• Good understanding of Fundamentals of Synchronous logic design.
• Good communication skills, positive attitude, and ability to work in a team environment.
• High GPA score (7.0 and above)
• A good command of English.
• Exposure to a scripting languages such as TCL, Perl, and/or C-shell is a plus.
• Prefer to working in Linux environment.
• Coursework in digital IC design is a plus.
• Prefer to experiencing with Verilog coding and verification.
• Project or industry experience in ASIC (Backend design: DFT, Layout, STA) is a plus.
• Prefer to understand process window & variation in semiconductor design

- 13th month salary; Bonus
- Healthcare
- Overseas travel opportunities

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